Invention Grant
US07881137B2 Read assist for memory circuits with different precharge voltage levels for bit line pair
有权
对位线对具有不同预充电电压电平的存储电路的读辅助
- Patent Title: Read assist for memory circuits with different precharge voltage levels for bit line pair
- Patent Title (中): 对位线对具有不同预充电电压电平的存储电路的读辅助
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Application No.: US12256569Application Date: 2008-10-23
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Publication No.: US07881137B2Publication Date: 2011-02-01
- Inventor: Nan Chen , Ritu Chaba
- Applicant: Nan Chen , Ritu Chaba
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle Gallardo; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.
Public/Granted literature
- US20100103755A1 Read Assist for Memory Circuits Public/Granted day:2010-04-29
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