Provided is an apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system are provided. In particular, an apparatus and method are provided which can reduce unnecessary time and power consumption by eliminating an unnecessary memory erasure. A write address generator generates write addresses. A memory stores values mapped to the write addresses. A memory controller controls the memory in which an input signal is accumulated to a value stored at a write address which is then recorded at the write address if the value stored at the write address is recorded for a previous packet when the input signal is generated. The memory controller controls the memory in which the input signal is recorded at the write address if the value stored at the current record address is a valid value for a current packet.