Invention Grant
- Patent Title: Optical lithography correction process
- Patent Title (中): 光学光刻校正过程
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Application No.: US11101872Application Date: 2005-04-09
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Publication No.: US07882456B2Publication Date: 2011-02-01
- Inventor: Franz Xaver Zach
- Applicant: Franz Xaver Zach
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Richter & Hampton LLP
- Agent Sheppard Mullin
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45
Abstract:
A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
Public/Granted literature
- US20060236271A1 Optical lithography correction process Public/Granted day:2006-10-19
Information query
