Invention Grant
- Patent Title: Wafer layout optimization method and system
- Patent Title (中): 晶圆布局优化方法和系统
-
Application No.: US12025213Application Date: 2008-02-04
-
Publication No.: US07882481B2Publication Date: 2011-02-01
- Inventor: Stefan Hempel
- Applicant: Stefan Hempel
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102007030051 20070629
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F19/00

Abstract:
For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is determined for each of the at least two wafer layouts. The at least one optimization parameter includes at least one of a number of exposure fields necessary for exposing the respective wafer layout and a number of die of the wafer layout. The optimized wafer layout is selected out of the at least two wafer layouts depending on the optimization parameter values.
Public/Granted literature
- US20090007028A1 WAFER LAYOUT OPTIMIZATION METHOD AND SYSTEM Public/Granted day:2009-01-01
Information query