Invention Grant
US07882482B2 Layout schemes and apparatus for high performance DC-DC output stage 有权
高性能DC-DC输出级的布局方案和设备

Layout schemes and apparatus for high performance DC-DC output stage
Abstract:
A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.
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