Invention Grant
US07882483B2 Method for checking constraints equivalence of an integrated circuit design
有权
用于检查集成电路设计的约束等效性的方法
- Patent Title: Method for checking constraints equivalence of an integrated circuit design
- Patent Title (中): 用于检查集成电路设计的约束等效性的方法
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Application No.: US11755764Application Date: 2007-05-31
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Publication No.: US07882483B2Publication Date: 2011-02-01
- Inventor: Sridhar Gangadharan , Manish Goel , Pratyush K. Prasoon , Suraj Bharech
- Applicant: Sridhar Gangadharan , Manish Goel , Pratyush K. Prasoon , Suraj Bharech
- Applicant Address: US CA San Jose
- Assignee: Atrenta, Inc.
- Current Assignee: Atrenta, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F17/50
Abstract:
The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.
Public/Granted literature
- US20080301598A1 METHOD FOR CHECKING CONSTRAINTS EQUIVALENCE OF AN INTEGRATED CIRCUIT DESIGN Public/Granted day:2008-12-04
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