Invention Grant
- Patent Title: Stacked die semiconductor package and method of assembly
- Patent Title (中): 堆叠半导体封装和组装方法
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Application No.: US12124880Application Date: 2008-05-21
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Publication No.: US07883938B2Publication Date: 2011-02-08
- Inventor: Ravi Kanth Kolan , Anthony Sun Yi Sheng , Liu Hao , Toh Chin Hock
- Applicant: Ravi Kanth Kolan , Anthony Sun Yi Sheng , Liu Hao , Toh Chin Hock
- Applicant Address: SG Singapore
- Assignee: United Test and Assembly Center Ltd.
- Current Assignee: United Test and Assembly Center Ltd.
- Current Assignee Address: SG Singapore
- Agency: Sughrue Mion, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.
Public/Granted literature
- US20090004777A1 Stacked die semiconductor package and method of assembly Public/Granted day:2009-01-01
Information query
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