Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a chip with a plurality of bond pads thereon; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, where at least one of the layers is configured to electrically connect a plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the chip, where the redistribution layer is configured to electrically connect at least one of the bond pad connectors and at least one of the bond pads on the chip. Such an approach enables reductions in overall package costs. The RDL may complete an electrical path between one or more substrate traces and the corresponding bond pad(s) to avoid increasing the substrate layer count. Because substrate layers are typically provided in pairs, the advantages of the invention may be amplified when a relatively small number of connections (e.g., one) are made via an RDL on the chip.