A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure. A first source region is formed adjacent the first gate structure, a common drain/cathode region is formed between the first and second gate structures, a second source region is formed adjacent the third gate structure, a common drain/source region is formed between the third and fourth gate structures, and a drain region is formed adjacent the fourth gate structure. A first base region is formed that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region is formed in the first well region that extends into the first well region adjacent the first base region.