Invention Grant
US07883950B2 Semiconductor device having reduced polysilicon pattern width and method of manufacturing the same
失效
具有降低的多晶硅图案宽度的半导体器件及其制造方法
- Patent Title: Semiconductor device having reduced polysilicon pattern width and method of manufacturing the same
- Patent Title (中): 具有降低的多晶硅图案宽度的半导体器件及其制造方法
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Application No.: US11875005Application Date: 2007-10-19
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Publication No.: US07883950B2Publication Date: 2011-02-08
- Inventor: Ji Ho Hong
- Applicant: Ji Ho Hong
- Applicant Address: KR Seoul
- Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Saliwanchik, Lloyd & Saliwanchik
- Priority: KR10-2006-0118810 20061129
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L21/44 ; H01L21/461
Abstract:
Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a spacer on a lateral side of the polysilicon layer, and forming a source/drain region in the substrate at sides of the spacer.
Public/Granted literature
- US20080122019A1 Semiconductor Device and Method of Manufacturing the Same Public/Granted day:2008-05-29
Information query
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