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US07883990B2 High resistivity SOI base wafer using thermally annealed substrate 有权
使用热退火基板的高电阻率SOI基底晶片

High resistivity SOI base wafer using thermally annealed substrate
Abstract:
A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.
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