Invention Grant
US07883990B2 High resistivity SOI base wafer using thermally annealed substrate
有权
使用热退火基板的高电阻率SOI基底晶片
- Patent Title: High resistivity SOI base wafer using thermally annealed substrate
- Patent Title (中): 使用热退火基板的高电阻率SOI基底晶片
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Application No.: US11931371Application Date: 2007-10-31
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Publication No.: US07883990B2Publication Date: 2011-02-08
- Inventor: Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
- Applicant: Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Steven Capella, Esq.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/46

Abstract:
A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.
Public/Granted literature
- US20090110898A1 HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE Public/Granted day:2009-04-30
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