Invention Grant
- Patent Title: Super high density module with integrated wafer level packages
- Patent Title (中): 具有集成晶圆级封装的超高密度模块
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Application No.: US11830377Application Date: 2007-07-30
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Publication No.: US07884007B2Publication Date: 2011-02-08
- Inventor: Yong Poo Chia , Suan Jeung Boon , Siu Waf Low , Yong Loo Neo , Bok Leng Ser
- Applicant: Yong Poo Chia , Suan Jeung Boon , Siu Waf Low , Yong Loo Neo , Bok Leng Ser
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Whyte Hirschboeck Dudek SC
- Priority: SG200203050-0 20020521
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.
Public/Granted literature
- US20070264751A1 Super High Density Module with Integrated Wafer Level Packages Public/Granted day:2007-11-15
Information query
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