Invention Grant
US07884465B2 Semiconductor package with passive elements embedded within a semiconductor chip
失效
具有嵌入半导体芯片内的无源元件的半导体封装
- Patent Title: Semiconductor package with passive elements embedded within a semiconductor chip
- Patent Title (中): 具有嵌入半导体芯片内的无源元件的半导体封装
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Application No.: US11778149Application Date: 2007-07-16
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Publication No.: US07884465B2Publication Date: 2011-02-08
- Inventor: Seung Taek Yang
- Applicant: Seung Taek Yang
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2007-0060262 20070620
- Main IPC: H01L23/04
- IPC: H01L23/04
Abstract:
A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip.
Public/Granted literature
- US20080315416A1 A SEMICONDUCTOR PACKAGE WITH PASSIVE ELEMENTS EMBEDDED WITHIN A SEMICONDUCTOR CHIP Public/Granted day:2008-12-25
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