Invention Grant
US07884473B2 Method and structure for increased wire bond density in packages for semiconductor chips
有权
用于半导体芯片的封装中增加引线键合密度的方法和结构
- Patent Title: Method and structure for increased wire bond density in packages for semiconductor chips
- Patent Title (中): 用于半导体芯片的封装中增加引线键合密度的方法和结构
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Application No.: US11850283Application Date: 2007-09-05
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Publication No.: US07884473B2Publication Date: 2011-02-08
- Inventor: Hsien-Wei Chen , Shih-Hsun Hsu
- Applicant: Hsien-Wei Chen , Shih-Hsun Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/49
- IPC: H01L23/49

Abstract:
A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.
Public/Granted literature
- US20090057902A1 METHOD AND STRUCTURE FOR INCREASED WIRE BOND DENSITY IN PACKAGES FOR SEMICONDUCTOR CHIPS Public/Granted day:2009-03-05
Information query
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