Invention Grant
US07884638B1 Techniques for providing calibrated on-chip termination impedance 有权
提供校准的片上终端阻抗的技术

  • Patent Title: Techniques for providing calibrated on-chip termination impedance
  • Patent Title (中): 提供校准的片上终端阻抗的技术
  • Application No.: US12236201
    Application Date: 2008-09-23
  • Publication No.: US07884638B1
    Publication Date: 2011-02-08
  • Inventor: Vikram SanturkarHyun Yi
  • Applicant: Vikram SanturkarHyun Yi
  • Applicant Address: US CA San Jose
  • Assignee: Altera Corporation
  • Current Assignee: Altera Corporation
  • Current Assignee Address: US CA San Jose
  • Agent Steven J. Cahill
  • Main IPC: H03K17/16
  • IPC: H03K17/16
Techniques for providing calibrated on-chip termination impedance
Abstract:
An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.
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