A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.