A Class D amplifier includes a ramp generator configured to generate a first signal and a second signal. Each of the first signal and the second signal oscillate between a minimum value and a maximum value. A signal generator is configured to receive an input signal, the first signal and the second signal. The input signal has a value that is between the minimum value and the maximum value. A signal generator is configured to generate a third signal and a fourth signal. The third signal is generated based on each of the first signal and the second signal transitioning from a value above the value of the input signal to a value below the value of the input signal. The fourth signal is generated based on each of the first signal and the second signal transitioning from a value below the value of the input signal to a value above the value of the input signal. An output stage is configured to drive a load based on the third signal and the fourth signal.