Invention Grant
US07885138B2 Three dimensional twisted bitline architecture for multi-port memory
失效
用于多端口存储器的三维扭转位线架构
- Patent Title: Three dimensional twisted bitline architecture for multi-port memory
- Patent Title (中): 用于多端口存储器的三维扭转位线架构
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Application No.: US11875173Application Date: 2007-10-19
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Publication No.: US07885138B2Publication Date: 2011-02-08
- Inventor: Hoki Kim , Toshiaki Kirihata
- Applicant: Hoki Kim , Toshiaki Kirihata
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Lisa Jaklitsch; Katherine S. Brown
- Main IPC: G11C8/00
- IPC: G11C8/00
Abstract:
Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
Public/Granted literature
- US20090103390A1 Three Dimensional Twisted Bitline Architecture for Multi-port Memory Public/Granted day:2009-04-23
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