Invention Grant
- Patent Title: Closed-loop modeling of gate leakage for fast simulators
- Patent Title (中): 用于快速模拟器的栅极泄漏的闭环建模
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Application No.: US11746976Application Date: 2007-05-10
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Publication No.: US07885798B2Publication Date: 2011-02-08
- Inventor: Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
- Applicant: Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Libby Z. Handelsman; Jack V. Musgrove
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F7/62

Abstract:
A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.
Public/Granted literature
- US20080281570A1 Closed-Loop Modeling of Gate Leakage for Fast Simulators Public/Granted day:2008-11-13
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