Invention Grant
US07886085B2 Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal
有权
可移动存储设备,相位同步方法,相位同步程序,介质记录和主机终端
- Patent Title: Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal
- Patent Title (中): 可移动存储设备,相位同步方法,相位同步程序,介质记录和主机终端
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Application No.: US12295051Application Date: 2007-02-20
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Publication No.: US07886085B2Publication Date: 2011-02-08
- Inventor: Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
- Applicant: Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2006-104039 20060405
- International Application: PCT/JP2007/053008 WO 20070220
- International Announcement: WO2007/113945 WO 20071011
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F3/00

Abstract:
An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
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