Invention Grant
- Patent Title: Semiconductor memory apparatus
- Patent Title (中): 半导体存储装置
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Application No.: US12042907Application Date: 2008-03-05
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Publication No.: US07886178B2Publication Date: 2011-02-08
- Inventor: Naoto Maeda
- Applicant: Naoto Maeda
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JP2007-057252 20070307
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G01R23/00 ; H03L7/06

Abstract:
In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit.
Public/Granted literature
- US20080218227A1 SEMICONDUCTOR MEMORY APPARATUS Public/Granted day:2008-09-11
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