Invention Grant
US07886242B1 Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs
有权
全面覆盖分析和电路设计排名的系统，方法和设备
- Patent Title: Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs
- Patent Title (中): 全面覆盖分析和电路设计排名的系统，方法和设备
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Application No.: US11842820Application Date: 2007-08-21
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Publication No.: US07886242B1Publication Date: 2011-02-08
- Inventor: Swapnajit Chakraborti , Sandeep Pagey , Boris Gommershtadt , Yael Duek-Golan
- Applicant: Swapnajit Chakraborti , Sandeep Pagey , Boris Gommershtadt , Yael Duek-Golan
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Alford Law Group, Inc.
- Agent William E. Alford
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
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