Invention Grant
- Patent Title: Stacked integrated circuit assembly
- Patent Title (中): 堆叠式集成电路组件
-
Application No.: US12557205Application Date: 2009-09-10
-
Publication No.: US07888176B2Publication Date: 2011-02-15
- Inventor: Tse E. Wong , Samuel D. Tonomura , Stephen E. Sox , Timothy E. Dearden , Clifton Quan , Polwin C. Chan , Mark S. Hauhe
- Applicant: Tse E. Wong , Samuel D. Tonomura , Stephen E. Sox , Timothy E. Dearden , Clifton Quan , Polwin C. Chan , Mark S. Hauhe
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.
Public/Granted literature
- US20100003785A1 STACKED INTEGRATED CIRCUIT ASSEMBLY Public/Granted day:2010-01-07
Information query
IPC分类: