Invention Grant
US07888201B2 Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
有权
使用部分耗尽和完全耗尽的晶体管配置的绝缘体上半导体SRAM
- Patent Title: Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
- Patent Title (中): 使用部分耗尽和完全耗尽的晶体管配置的绝缘体上半导体SRAM
-
Application No.: US11789616Application Date: 2007-04-25
-
Publication No.: US07888201B2Publication Date: 2011-02-15
- Inventor: Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
- Applicant: Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/148
- IPC: H01L27/148
Abstract:
A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.
Public/Granted literature
- US20070264762A1 Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors Public/Granted day:2007-11-15
Information query
IPC分类:
