Invention Grant
US07888238B2 Method of manufacturing semiconductor device having semiconductor formation regions of different planar sizes
有权
具有不同平面尺寸的半导体形成区域的半导体器件的制造方法
- Patent Title: Method of manufacturing semiconductor device having semiconductor formation regions of different planar sizes
- Patent Title (中): 具有不同平面尺寸的半导体形成区域的半导体器件的制造方法
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Application No.: US12330745Application Date: 2008-12-09
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Publication No.: US07888238B2Publication Date: 2011-02-15
- Inventor: Shinji Wakisaka , Norihiko Kaneko
- Applicant: Shinji Wakisaka , Norihiko Kaneko
- Applicant Address: JP Tokyo
- Assignee: Casio Computer Co., Ltd.
- Current Assignee: Casio Computer Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick, PC
- Priority: JP2007-320303 20071212
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A wafer process material is prepared which has a plurality of semiconductor formation regions of different planar sizes, each including a low dielectric constant film/wiring line stack structure component. A laser beam is applied onto a dicing street of the necessary semiconductor formation region and onto its straight extension in order to remove partial areas of the low dielectric constant film/wiring line stack structure components of the necessary semiconductor formation region and the unnecessary semiconductor formation region so that first groove and the second groove are formed. A protective film is formed in the second groove formed in the unnecessary semiconductor formation region and on the low dielectric constant film/wiring line stack structure component. An upper wiring line and a sealing film are formed on the protective film, and a semiconductor wafer is cut along the dicing street.
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