Invention Grant
US07888638B2 Method and apparatus for measuring dimension of circuit pattern formed on substrate by using scanning electron microscope
有权
使用扫描电子显微镜测量在基片上形成的电路图形尺寸的方法和装置
- Patent Title: Method and apparatus for measuring dimension of circuit pattern formed on substrate by using scanning electron microscope
- Patent Title (中): 使用扫描电子显微镜测量在基片上形成的电路图形尺寸的方法和装置
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Application No.: US12354923Application Date: 2009-01-16
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Publication No.: US07888638B2Publication Date: 2011-02-15
- Inventor: Atsushi Miyamoto , Tomofumi Nishiura
- Applicant: Atsushi Miyamoto , Tomofumi Nishiura
- Applicant Address: JP Tokyo
- Assignee: Hitachi High-Technologies Corporation
- Current Assignee: Hitachi High-Technologies Corporation
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2008-089131 20080331
- Main IPC: G01N23/00
- IPC: G01N23/00 ; G21K7/00

Abstract:
In the dimension measurement of a circuit pattern using a scanning electron microscope (SEM), in order to make it possible to automatically image desired evaluation points (EPs) on a sample, and automatically measure the circuit pattern formed at the evaluation points, according to the present invention, in the dimension measurement of a circuit pattern using a scanning electron microscope (SEM), it is arranged that coordinate data of the EP and design data of the circuit pattern including the EP are used as an input, creation of a dimension measurement cursor for measuring the pattern existing in the EP and selection or setting of the dimension measurement method are automatically performed based on the EP coordinate data and the design data to automatically create a recipe, and automatic imaging/measurement is performed using the recipe.
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