Invention Grant
- Patent Title: Integrated complementary low voltage RF-LDMOS
- Patent Title (中): 集成互补低压RF-LDMOS
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Application No.: US12553464Application Date: 2009-09-03
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Publication No.: US07888735B2Publication Date: 2011-02-15
- Inventor: Jun Cai
- Applicant: Jun Cai
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Hiscock & Barclay, LLP
- Agent Thomas R. FitzGerald, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.
Public/Granted literature
- US20100013012A1 INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS Public/Granted day:2010-01-21
Information query
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