Invention Grant
- Patent Title: Micro-layered lead frame semiconductor packages
- Patent Title (中): 微层引线框半导体封装
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Application No.: US12199065Application Date: 2008-08-27
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Publication No.: US07888781B2Publication Date: 2011-02-15
- Inventor: Manolito Galera , Leocadio Morona Alabin
- Applicant: Manolito Galera , Leocadio Morona Alabin
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Agency: Kirton & McConkie
- Agent Kenneth Horton
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame with a customized array of lands at the bottom of the package. The lands are connected to a series of leads that are located within the perimeter of the lands. The leads can be routed according to the requirements of each specific IC die which they support and therefore can support both a single die and multiple die in the semiconductor package. Such a configuration provides a flexible routing for optimized layout, a maximized package density, and a higher input/output capability with a smaller package size. Other embodiments are also described.
Public/Granted literature
- US20100052118A1 MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGES Public/Granted day:2010-03-04
Information query
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