Invention Grant
- Patent Title: Semiconductor device package of stacked semiconductor chips with spacers provided therein
- Patent Title (中): 具有间隔件的层叠半导体芯片的半导体器件封装
-
Application No.: US11934976Application Date: 2007-11-05
-
Publication No.: US07888805B2Publication Date: 2011-02-15
- Inventor: Kou Sasaki
- Applicant: Kou Sasaki
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2004-048992 20040225
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than the first spacer, flexure of the upper semiconductor chip can be avoided.
Public/Granted literature
- US20080087989A1 SEMICONDUCTOR DEVICE PACKAGE OF STACKED SEMICONDUCTOR CHIPS WITH SPACERS PROVIDED THEREIN Public/Granted day:2008-04-17
Information query
IPC分类:
