Invention Grant
- Patent Title: Read operation for NAND memory
- Patent Title (中): NAND存储器的读操作
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Application No.: US12582289Application Date: 2009-10-20
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Publication No.: US07889561B2Publication Date: 2011-02-15
- Inventor: Seiichi Aritome , Akira Goda
- Applicant: Seiichi Aritome , Akira Goda
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04

Abstract:
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell.
Public/Granted literature
- US20100039862A1 READ OPERATION FOR NAND MEMORY Public/Granted day:2010-02-18
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