Invention Grant
- Patent Title: Jitter estimation in phase-locked loops
- Patent Title (中): 锁相环中的抖动估计
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Application No.: US12189744Application Date: 2008-08-11
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Publication No.: US07890279B1Publication Date: 2011-02-15
- Inventor: Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
- Applicant: Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.
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