Invention Grant
US07890900B2 Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer
有权
用于有效提高具有每个晶片存储器的芯片模具的各种方法和装置
- Patent Title: Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer
- Patent Title (中): 用于有效提高具有每个晶片存储器的芯片模具的各种方法和装置
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Application No.: US12194454Application Date: 2008-08-19
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Publication No.: US07890900B2Publication Date: 2011-02-15
- Inventor: Karen Aleksanyan , Valery Vardanian , Yervant Zorian
- Applicant: Karen Aleksanyan , Valery Vardanian , Yervant Zorian
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.
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