Invention Grant
US07897450B2 Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures
有权
通过在两个不同的工艺温度下形成衬套来封装高K栅极堆叠的方法
- Patent Title: Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures
- Patent Title (中): 通过在两个不同的工艺温度下形成衬套来封装高K栅极堆叠的方法
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Application No.: US12355250Application Date: 2009-01-16
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Publication No.: US07897450B2Publication Date: 2011-03-01
- Inventor: Fabian Koehler , Katy Schabernack , Falk Graetsch
- Applicant: Fabian Koehler , Katy Schabernack , Falk Graetsch
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson
- Priority: DE102008016437 20080331
- Main IPC: H01L21/8249
- IPC: H01L21/8249

Abstract:
Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.
Public/Granted literature
- US20090242999A1 METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES Public/Granted day:2009-10-01
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