Invention Grant
- Patent Title: Method for manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12142011Application Date: 2008-06-19
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Publication No.: US07897466B2Publication Date: 2011-03-01
- Inventor: Yuji Akao
- Applicant: Yuji Akao
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2007-162448 20070620
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole.
Public/Granted literature
- US20080318393A1 Method for Manufacturing Semiconductor Device Public/Granted day:2008-12-25
Information query
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