Invention Grant
- Patent Title: Fabricating a top conductive layer in a semiconductor die
- Patent Title (中): 在半导体管芯中制造顶部导电层
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Application No.: US12462436Application Date: 2009-08-03
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Publication No.: US07897484B2Publication Date: 2011-03-01
- Inventor: Arjun Kar-Roy , Marco Racanelli , David J. Howard
- Applicant: Arjun Kar-Roy , Marco Racanelli , David J. Howard
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.
Public/Granted literature
- US20090298285A1 Fabricating a Top Conductive Layer in a Semiconductor Die Public/Granted day:2009-12-03
Information query
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