Invention Grant
US07897485B2 Wafer processing including forming trench rows and columns at least one of which has a different width
有权
晶片处理包括形成沟槽行和列，其中至少一个具有不同的宽度
- Patent Title: Wafer processing including forming trench rows and columns at least one of which has a different width
- Patent Title (中): 晶片处理包括形成沟槽行和列，其中至少一个具有不同的宽度
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Application No.: US12504385Application Date: 2009-07-16
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Publication No.: US07897485B2Publication Date: 2011-03-01
- Inventor: Kunal R. Parekh
- Applicant: Kunal R. Parekh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huesbch, PLLC
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/78 ; H01L21/301
Abstract:
Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on side walls of the number of trenches. The method also includes cutting a second side of the semiconductor wafer in rows and columns aligned with the number of trenches such that the semiconductor wafer singulates into a number of dice.
Public/Granted literature
- US20090280584A1 WAFER PROCESSING Public/Granted day:2009-11-12
Information query
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