Invention Grant
US07898019B2 Semiconductor constructions having multiple patterned masking layers over NAND gate stacks
有权
在NAND门叠层上具有多个图案化掩模层的半导体结构
- Patent Title: Semiconductor constructions having multiple patterned masking layers over NAND gate stacks
- Patent Title (中): 在NAND门叠层上具有多个图案化掩模层的半导体结构
-
Application No.: US12331059Application Date: 2008-12-09
-
Publication No.: US07898019B2Publication Date: 2011-03-01
- Inventor: David J. Keller , Hongbin Zhu , Alex J. Schrinsky
- Applicant: David J. Keller , Hongbin Zhu , Alex J. Schrinsky
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/788
- IPC: H01L29/788
Abstract:
Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.
Public/Granted literature
- US20090090958A1 Semiconductor Constructions Public/Granted day:2009-04-09
Information query
IPC分类:
