Invention Grant
- Patent Title: Pre-molded, clip-bonded multi-die semiconductor package
- Patent Title (中): 预成型,夹式多芯片半导体封装
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Application No.: US12262486Application Date: 2008-10-31
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Publication No.: US07898067B2Publication Date: 2011-03-01
- Inventor: Armand Vincent C. Jereza
- Applicant: Armand Vincent C. Jereza
- Assignee: Fairchild Semiconductor Corporaton
- Current Assignee: Fairchild Semiconductor Corporaton
- Agency: Kirton & McConkie
- Agent Kenneth Horton
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.
Public/Granted literature
- US20100109134A1 PRE-MOLDED, CLIP-BONDED MULTI-DIE SEMICONDUCTOR PACKAGE Public/Granted day:2010-05-06
Information query
IPC分类: