Invention Grant
US07898286B2 Critical path redundant logic for mitigation of hardware across chip variation
有权
用于缓解跨芯片变化的硬件的关键路径冗余逻辑
- Patent Title: Critical path redundant logic for mitigation of hardware across chip variation
- Patent Title (中): 用于缓解跨芯片变化的硬件的关键路径冗余逻辑
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Application No.: US12369066Application Date: 2009-02-11
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Publication No.: US07898286B2Publication Date: 2011-03-01
- Inventor: Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
- Applicant: Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole. P.C.
- Agent David Cain
- Main IPC: H03K19/00
- IPC: H03K19/00
Abstract:
Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
Public/Granted literature
- US20100201377A1 Critical Path Redundant Logic for Mitigation of Hardware Across Chip Variation Public/Granted day:2010-08-12
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