Invention Grant
US07898288B2 Input termination for delay locked loop feedback with impedance matching
有权
具有阻抗匹配的延迟锁定环路反馈的输入端接
- Patent Title: Input termination for delay locked loop feedback with impedance matching
- Patent Title (中): 具有阻抗匹配的延迟锁定环路反馈的输入端接
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Application No.: US11608234Application Date: 2006-12-07
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Publication No.: US07898288B2Publication Date: 2011-03-01
- Inventor: Tak Kwong Wong
- Applicant: Tak Kwong Wong
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, inc.
- Current Assignee: Integrated Device Technology, inc.
- Current Assignee Address: US CA San Jose
- Agency: Bever Hoffman & Harms LLP
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.
Public/Granted literature
- US20080136443A1 Input Termination For Delay Locked Loop Feedback With Impedance Matching Public/Granted day:2008-06-12
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