Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US12651061Application Date: 2009-12-31
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Publication No.: US07898305B2Publication Date: 2011-03-01
- Inventor: Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
- Applicant: Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-260831 20050908
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
Public/Granted literature
- US20100171533A1 PLL CIRCUIT Public/Granted day:2010-07-08
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