A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.