A resistance change memory includes first and second memory cell arrays which are adjacent to each other in a first direction, first and second reference cell arrays paired with the first and second memory cell arrays, a first sense amplifier shared by the first and second memory cell arrays and arranged between the first and second memory cell arrays, a first data bus which transfers data of a first readout cell in the first memory cell array to the first sense amplifier, and a second data bus which transfers data of a first reference cell in the first reference cell array to the first sense amplifier. The first and second data buses run on both sides of the first sense amplifier in a second direction and cross each other while sandwiching the first sense amplifier.