Invention Grant
US07898851B2 Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
有权
半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元
- Patent Title: Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
- Patent Title (中): 半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元
-
Application No.: US11960158Application Date: 2007-12-19
-
Publication No.: US07898851B2Publication Date: 2011-03-01
- Inventor: Hiroshi Maejima , Makoto Hamada
- Applicant: Hiroshi Maejima , Makoto Hamada
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C7/00
Abstract:
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit.
Public/Granted literature
- US20090159949A1 SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE Public/Granted day:2009-06-25
Information query
