Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US12410868Application Date: 2009-03-25
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Publication No.: US07898896B2Publication Date: 2011-03-01
- Inventor: Atsushi Miyanishi
- Applicant: Atsushi Miyanishi
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-246408 20050826
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.
Public/Granted literature
- US20090185431A1 SEMICONDUCTOR DEVICE Public/Granted day:2009-07-23
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