Invention Grant
- Patent Title: Method and apparatus for creating a gate optimization evaluation library
- Patent Title (中): 用于创建门优化评估库的方法和装置
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Application No.: US11762563Application Date: 2007-06-13
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Publication No.: US07899637B2Publication Date: 2011-03-01
- Inventor: Asao Yamashita , Merritt Funk , Daniel Prager , Lee Chen , Radha Sundararajan
- Applicant: Asao Yamashita , Merritt Funk , Daniel Prager , Lee Chen , Radha Sundararajan
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: B21D22/00
- IPC: B21D22/00
Abstract:
The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
Public/Granted literature
- US20080311688A1 Method and Apparatus for Creating a Gate Optimization Evaluation Library Public/Granted day:2008-12-18
Information query
