Invention Grant
- Patent Title: Integrated circuit characterisation system and method
- Patent Title (中): 集成电路表征系统及方法
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Application No.: US12183298Application Date: 2008-07-31
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Publication No.: US07899640B2Publication Date: 2011-03-01
- Inventor: Vyacheslav L. Zavadsky , Mykola Sherstyuk
- Applicant: Vyacheslav L. Zavadsky , Mykola Sherstyuk
- Applicant Address: CA Kanata
- Assignee: Semiconductor Insights Inc.
- Current Assignee: Semiconductor Insights Inc.
- Current Assignee Address: CA Kanata
- Agency: Hoffman Warnick LLC
- Agent John W. LaBatt
- Main IPC: G06F11/26
- IPC: G06F11/26 ; G06F11/00

Abstract:
There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.
Public/Granted literature
- US20100030497A1 INTEGRATED CIRCUIT CHARACTERISATION SYSTEM AND METHOD Public/Granted day:2010-02-04
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