Invention Grant
- Patent Title: CPU datapipe architecture with crosspoint switch
- Patent Title (中): 具有交叉点开关的CPU数据通道架构
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Application No.: US11322487Application Date: 2005-12-30
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Publication No.: US07899857B2Publication Date: 2011-03-01
- Inventor: Jerry W. Yancey
- Applicant: Jerry W. Yancey
- Applicant Address: US NY New York
- Assignee: L3 Communications Corporation
- Current Assignee: L3 Communications Corporation
- Current Assignee Address: US NY New York
- Agency: Lathrop & Gage LLP
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.
Public/Granted literature
- US20070198810A1 CPU datapipe architecture with crosspoint switch Public/Granted day:2007-08-23
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