Invention Grant
US07900104B2 Test pattern compression for an integrated circuit test environment
有权
用于集成电路测试环境的测试模式压缩
- Patent Title: Test pattern compression for an integrated circuit test environment
- Patent Title (中): 用于集成电路测试环境的测试模式压缩
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Application No.: US12405409Application Date: 2009-03-17
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Publication No.: US07900104B2Publication Date: 2011-03-01
- Inventor: Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
- Applicant: Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Klarquist Sparkman, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
Public/Granted literature
- US20090259900A1 TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT Public/Granted day:2009-10-15
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