Invention Grant
- Patent Title: Temporal decomposition for design and verification
- Patent Title (中): 设计和验证的时间分解
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Application No.: US12345473Application Date: 2008-12-29
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Publication No.: US07900173B1Publication Date: 2011-03-01
- Inventor: Andreas Kuehlmann , Xiaoqun Du
- Applicant: Andreas Kuehlmann , Xiaoqun Du
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
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